The present invention relates to an integrated digital MOS semiconductor circuit which has an input to be charged by signals having differing levels. A first operating mode can be initiated on the basis of the signals having one level and a second operating mode can be initiated with a second level upon simultaneous shutdown of the other operating mode under given conditions.
Such a design of an integrated digital MOS semiconductor circuit would be of significance, for example, for integrated MOS semiconductor memories having redundant rows and columns--particularly for dynamic memories of this type. As known, the matrix of such memories comprises additional rows and columns which are initially not provided for the normal operation of the memory. When, however, a malfunction occurs at a memory cell provided for normal operation, then there is the possibility of replacing the row or column containing the malfunctioning cell with a redundant row or column. The redundant row or column is then made accessible for normal operation from which it had initially been inhibited by means of a corresponding manipulation whereas, on the other hand, the row or column containing the malfunctioning cell is permanently shut down. For this purpose, it is standard to keep the redundant rows and columns from responding during normal operation by means of disconnectible connections. The activation of the redundant row or column then likewise occurs by means of cutting these short-circuit connections. It is thus frequently necessary to have a possibility available for the recognition of those rows and columns of the memory matrix that have been replaced by a redundant row or column.
German patent application P 33 11 427.7, incorporated herein by reference, discloses an integrated dynamic write/read memory that is designed such that the replacement of a row or column of the memory matrix that is provided for normal operation by a redundant row or column is detected by means of a logic level at the data output given a charging with control signals that corresponds to the so-called roll-call mode in static memories. The possibility then exists of applying such control signals for testing to signal connections of the memory circuit that are especially provided therefor. This, however, leads to an added expense of terminal pins for the IC module containing the memory which is undesirable for known reasons. However, differently set signals can also be employed for the normal mode on the one hand and for the test mode on the other hand, these being applied to a common external signal input. When one has signals of the one level, these lead to the one operating mode and when one has signals of the other level, then these automatically lead to the other operating mode as a consequence of a corresponding internal layout of the integrated circuit. Required for this purpose is a changeover system effecting the changeover which automatically determines on the basis of a signal applied to the common external signal input to be charged by the two types of signals whether the applied signal is intended for the normal mode or for the test mode. On the basis of this signal, a corresponding internal setting of the circuit to the test mode or to the normal mode occurs.
The circuit parts in the integrated circuit that are provided for the test functions can, for example, thus be activated in that a signal input electrode which is internally connected in the manner indicated for the test mode is charged with a signal voltage that is higher than the normal operating voltage of the IC module. It must thereby be assured, however, that the test function cannot be initiated by a signal voltage provided for the normal operation at the signal connection. On the other hand, the voltage for the test signal must still lie below the maximum allowable voltage charge of the integrated circuit for understandable reasons. Furthermore, a current flux across the input should be avoided when the input is connected to the test signal. It is also desirable for the test mode to occur only when circuit parts provided for the normal mode have been previously replaced in the module by redundant circuit parts, so that an absolute shutdown of the circuit parts provided for the test mode previous thereto is provided. The possibility thus results that, given ICs equipped with redundancy and designed identically to one another circuit-wise, those where redundant parts have already been engaged into the normal mode can be distinguished in a simple manner from those where this is not the case.